What You Will Build
Compiler Architecture & Intermediate Representations
- 🔹Architect and evolve our client's compiler IR strategy, building on MLIR/LLVM infrastructure to lower high-
level ML graphs into hardware-aware representations for RISC-V and AI accelerator execution
- 🔹Design and own custom dialects, optimization passes, and lowering pipelines that map cleanly onto ASHAI's
vector and accelerator ISA extensions
- 🔹Set the multi-year technical roadmap for the compiler stack, balancing near-term customer performance
commitments against long-term platform scalability
Graph-Level Optimization & Performance Engineering
- 🔹Drive graph transformations, operator fusion, pattern rewriting, quantization, and memory planning strategies
that materially reduce latency and increase throughput on our client's hardware
- 🔹Own performance benchmarking of the compiler stack against GPU baselines: tokens per second, cost per
token, and memory efficiency
- 🔹Profile, debug, and tune computational kernels, including matrix multiplication, attention, and other core
inference operators, to close the gap between theoretical and achieved performance
Toolchain, SDK & Developer Platform
- 🔹Design, build, and maintain a scalable, production-grade compiler toolchain and SDK APIs that customers use
to compile and deploy models on our client's hardware
- 🔹Own RISC-V toolchain integration: compiler support, ABI compatibility, and build system tooling for ASHAI-
optimized binaries
- 🔹Establish automated testing, benchmarking, and CI/CD infrastructure that keeps the compiler stack stable as it
scales Team Building & Technical Leadership
- 🔹Recruit, hire, and lead a world-class compiler engineering team from the ground up, setting hiring bar, technical
direction, and career growth paths
- 🔹Guide engineers through code review, design review, and mentorship practices that keep the codebase and team
execution at a high standard
- 🔹Evaluate and integrate learning-based and agent-assisted approaches into the compilation pipeline and the
team's own development practices where they measurably improve outcomes
Hardware/Software Co-Design & Cross-Functional Collaboration
- 🔹Partner directly with the SoC Architecture team to align compiler capabilities with the constraints and
opportunities of our client's custom silicon, informing ISA extension and microarchitecture decisions
- 🔹Partner with the VP, System & Applications Engineering on the boundary between the compiler stack and the
runtime, HAL, and…